A transconductance circuit is a practical realization of a voltage-controlled current source. Transconductance circuits find application in active filters, gyrators, oscillators and impedance transformers. Linearity is one parameter affecting transconductance circuit utility, because nonlinearities give rise to undesirable effects such as distortion.
U.S. Pat. No. 5,576,646, entitled "Transconductance Circuit With High-Linearity Double Input And Active Filter Thereof", issued to F. Rezzi et al., describes one solution to many of these problems. FIG. 1 is a simplified schematic diagram of a linearized transconductance circuit 10 taught by Rezzi et al., in accordance with the prior art. The transconductance circuit 10 includes first and second MOS FETs 12 and 14, having their sources coupled together at a first node 16, their drains coupled together at a second node 18 and their gates each coupled to one of inputs 20 and 22. The voltage at the first node 16 is a constant voltage and may be ground. A bipolar transistor 24 has an emitter coupled to the second node 18, a base coupled to a low impedance voltage source V.sub.DC that provides a constant voltage and a collector coupled to a constant current source 26 and to an output 28.
The transconductance circuit 10 uses the fact that a forward-biased emitter-base junction manifests a voltage that is well approximated by a piecewise linear model that assumes zero conduction below a threshold base-emitter voltage V.sub.BE of 0.7 volts, and that assumes a constant base-emitter voltage V.sub.BE of 0.7 volts after the base begins to conduct current. When this approximation is applied to the transistor 24, the drain-source voltage V.sub.DS of the MOS FETs 12 and 14 is approximated as V.sub.DS =V.sub.DC -0.7 volts-V.sub.NODE 16, where V.sub.DC represents a voltage from the source V.sub.DC and V.sub.NODE 16 represents the voltage at the node 16. As a result, the drain-source voltage V.sub.DS of the MOS FETs 12 and 14 is relatively constant, even with changes in operating current, reducing distortion effects due to variation in characteristics of the MOS FETs 12 and 14 with changing drain-source voltage V.sub.DS.
However, the emitter-base junction voltage V.sub.BE of the transistor 24 corresponds to the voltage drop across a forward-biased diode and is actually given as: EQU V.sub.BE =V.sub.TH ln(I.sub.C /I.sub.o), (Eq. 1)
where V.sub.TH represents a temperature-dependent variable, I.sub.o represents a constant that is a function of transistor (or diode) material and geometry and I.sub.C represents collector (or diode) current. Base-emitter voltage V.sub.BE variations, due to changes in collector current, give rise to drain-source voltage V.sub.DS variations for the FETs 12 and 14, and result in the dominant nonlinearities encountered with the transconductance circuit 10 of FIG. 1.